The present invention relates generally to a phase change memory device, and more particularly, to a memory device that has a phase change resistor which exhibits improved sensing performance and reliability due to resistance to memory cell degradation processes.
Some well known nonvolatile memory storage devices include magnetic memory and phase change memory (PCM) devices. The PCM devices can exhibit data processing speeds similar to that of a volatile Random Access Memory (RAM) device. Further PCM devices enjoy the advantage of being able to conserve or maintain data even after the power is turned off.
FIGS. 1a and 1b are diagrams illustrating a conventional phase change resistor (PCR) 4.
The conventional PCR 4 comprises a phase change material (PCM) 2 inserted between a top electrode 1 and a bottom electrode 3. When a voltage and a current are imposed across the top and bottom electrodes (1,3) the temperature is raised in the PCM 2 which can result in altering the electric conductive properties and thereby the resistance changes as a function of the resultant solid state morphology.
PCM 2 devices can include the chalcogenide AgLnSbTe. The PCM 2 often times includes a chalcogenide having at least one of the chalcogen elements (S, Se, Te) as a main ingredient, and containing other ingredients such as germanium and antimony. One PCM 2 of to interest is the germanium antimonic tellurium consisting of Ge—Sb—Te (Ge2Sb2Te5).
FIGS. 2a and 2b are diagrams illustrating a principle of the conventional PCR 4.
As shown in FIG. 2a, the PCM 2 can change its solid state crystalline structure, i.e., can become crystallized, when a low current of less than a threshold value flows in the PCM 4. As a result, of the highly order crystalline lattice morphology of the PCM 2, this crystallized form of the PCM 2 exhibits a relatively low resistance.
As shown in FIG. 2b, the crystalline morphological state of the PCM 2 can be induced to melt when a current of more than a threshold value is imposed across the PCR 4. As a result of raising the temperature above the crystalline melting temperature coupled by a relatively rapid cooling period of the melted PCM 2, the solid state morphology of the PCM 2 can be transformed into an alternate chaotic ordered solid state of being an amorphous morphology. It is though that because of the increased number or increased density of crystal imperfections in this amorphous state, the amorphous PCM 2 exhibits a relatively higher electrical resistance, as compared to the PCM 2 in a crystalline state.
Accordingly, one can exploit this difference in physical properties by designing a PCR 4 to be configured to store nonvolatile data corresponding to the two resistance states. One could arbitrarily assign a data “1” state to refer to when the PCR 4 exhibits a relatively low resistance state. Likewise, one could arbitrarily assign a data “0” state to refer to when the PCR 4 exhibits a relatively high resistance state. Accordingly, binary logic states can be stored in these types of PCM devises without the need for perpetually powering these devices.
FIG. 3 is a diagram illustrating a write operation of a conventional phase change resistant cell.
When heat is generated from an electrical current flowing across the top electrode 1 and the bottom electrode 3 of the PCR 4, the solid state morphology of the PCM 2 can be transformed back and forth from a crystalline to an amorphous solid state when the heat is raised above the melting point.
In contrast, when heat is generated from an low amount of electrical current flowing across the top electrode 1 and the bottom electrode 3 of the PCR 4, the solid state morphology of the PCM 2 in the crystalline morphological state can be maintained, regardless of being the crystalline or amorphous solid states. In contrast, when heat is generated from a slightly higher amount of electrical current flowing across the top electrode 1 and the bottom electrode 3 of the PCR 4, the solid state morphology of the PCM 2 in the crystalline state can be altered. As long as the melted PCM can be gently or slowly annealed the PCM can be either maintained or transformed into the crystalline morphological solid state. As a result of imposing this low temperature heating condition, the resultant PCR 4 exhibits a low resistor which can be arbitrarily defined to be a set state. On the other hand, when a relatively higher electrical current flows across the top electrode 1 and the bottom electrode 3 of the PCR 4, the PCM be transformed into an amorphous morphological solid state from the heating and from the relatively rapid cooling. As a consequence when the PCR 4 in the amorphous state it exhibits a relatively higher resistance which can be arbitrarily defined as a reset state. A physical property difference between these two morphological solid state phases is thought to be the responsible cause for the changes in the electric resistance.
A low voltage is applied to the PCR 4 for a long time in order to allow the PCM 2 to transform into the crystalline state and thus write the set state in a write mode. On the other hand, a high voltage is applied to the PCR 4 for a short time in order to allow the melted PCM 2 to rapidly cool into the amorphous state and thus write the reset state in the write mode.
However, the conventional phase change memory device distinguishes data with the same reference voltage in a read mode and in a write verifying mode. As a result, the stability of write data operation can be degraded in the write verifying mode due to cell degradation. In the read mode, a margin of a sensing voltage is reduced.